In recent years, research interest has focussed on adequate hardware circuit design. According to this design methodology, a circuit architecture is designed to be reconfigurable at runtime such that it can support multiple accuracy settings. This leads to corresponding power benefits at lower accuracies. Indeed, the longest and thus most critical timing paths of a processing circuit generally concern the least significant bit (LSB) of input data. Thus by reducing the number of bits of input data of the processing circuit that are processed, for example from 32 bits to 16 bits or less, certain operating conditions of the circuit can be relaxed, such as the supply voltage, leading to reduced power consumption, and/or the operating frequency can be increased. Power reduction also results from reduced switching activity in view of the unused input bits.
For example, the publication by Bert Moons and Marian Verhelst entitled “DVAS: Dynamic Voltage Accuracy Scaling for Increased Energy-Efficiency in Approximate Computing”, ISLPED, p. 237-242, Rome, 2015, proposes a technique allowing runtime-reconfigurable accuracy. In particular, DVAS consists in concurrently scaling the supply voltage of a circuit and reducing the number of used input bits. The bit width reduction allows to cope with the increased timing delay due to voltage scaling, by avoiding stimulation of the longest timing paths in the circuit.
The main limitation of DVAS systems is the phenomenon known as “Wall-of-Slack”, according to which, during synthesis, cells that belong to short paths are optimized for power and area by downsizing them. This leads to creating many “almost critical” paths, and therefore as soon as the supply voltage is reduced, timing violations will occur in a large percentage of the total paths.
Another limitation of DVAS is that, due to the different parts of the circuit operating at different supply voltages, it becomes necessary to insert level shifters at different places in the circuit design, adding complexity, power consumption and surface area.